A new compact analog vlsi model for spike timing dependent plasticity
Conference Publication ResearchOnline@JCUAbstract
Spike Timing Dependent Plasticity (STDP) is a time-based synaptic plasticity rule that has generated significant interest in the area of neuromorphic engineering and Very Large Scale Integration (VLSI) circuit design. During the last decade, STDP and STDP-like learning mechanisms have shown promising solutions for various real world applications, ranging from pattern recognition to robotics. This paper presents a novel analog VLSI model for STDP that possesses advantages compared to previously published VLSI STDP designs. The presented STDP circuit is capable of reproducing the outcomes of several well known experiments using various plasticity rules inducing STDP protocols that utilise pairs, triplets, and quadruplets of spike patterns. When the circuit is compared to state-of-the-art VLSI STDP circuits, it shows a compact and symmetric design that makes the proposed circuit a powerful component for use in designing STDP or time-based Hebbian learning experiments and applications.
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Publication Name
2013 IFIP/IEEE: 21st International Conference on Very Large Scale Integration (VLSI-SoC)
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ISBN/ISSN
978-1-4799-0524-9
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Pages Count
6
Location
Istanbul, Turkey
Publisher
Institute of Electrical and Electronics Engineers
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Publisher Location
Piscataway, NJ, USA
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Date
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DOI
10.1109/VLSI-SoC.2013.6673236