Physical implementation of pair-based spike-timing-dependent plasticity
Journal Contribution ResearchOnline@JCUAbstract
Objective Spike-timing-dependent plasticity (STDP) is one of several plasticity rules which leads to learning and memory in the brain. STDP induces synapticweight changes based on the timing of the pre- and postsynaptic neurons. A neural network which can mimic the adaptive capability of biological brains in the temporal domain, requires the weight of single connections to be altered by spike timing. To physically realise this network into silicon, a large number of interconnected STDP circuits on the same substrate is required. This imposes two significant limitations in terms of power and area. To cover these limitations, very large scale integrated circuit (VLSI) technology provides attractive features in terms of low power and small area requirements. An example is demonstrated by (Indiveri et al. 2006). The objective of this paper is to present a newimplementation of the STDPcircuit which demonstrates better power and area in comparison to previous implementations. Methods The proposed circuit uses complementary metal oxide semiconductor (CMOS) technology as depicted in Fig. 1. The synaptic weight can be stored on a capacitor and charging/discharging current can lead to potentiation and depression. Results and Conclusion: HSpice simulation results demonstrate that the average power, peak power, and area of the proposed circuit have been reduced by 6, 8 and 15%, respectively, in comparison with Indiveri's implementation. These improvements naturally lead to packing more STDP circuits onto the same substrate, when compared to previous proposals. Hence, this new implementation is quite interesting for real-world large neural networks.
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Publication Name
Australasian Physical & Engineering Sciences in Medicine
Volume
34
ISBN/ISSN
1879-5447
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Pages Count
1
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Publisher
Springer
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DOI
10.1007/s13246-011-0098-9